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NXP Semiconductors /LPC18xx /CCU1 /CLK_M3_EMCDIV_STAT

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Interpret as CLK_M3_EMCDIV_STAT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RUN)RUN 0 (AUTO)AUTO 0 (WAKEUP)WAKEUP 0RESERVED 0 (DIVIDEBY1)DIV0RESERVED

DIV=DIVIDEBY1

Description

CLK_M3_EMCDIV clock status register

Fields

RUN

Run enable status 0 = clock is disabled. 1 = clock is enabled.
AUTO

Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.
WAKEUP

Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.
RESERVED

Reserved
DIV

Clock divider value

0 (DIVIDEBY1): No division. Divide by 1.

1 (DIVIDEBY2): Divide by 2.
RESERVED

Reserved

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data